译码器是计算机系统中最常用的逻辑部件之一，用来完成对操作码的译码。
实验目的
练习用标准 74 系列器件设计组合电路。
实验内容
1.设计一个 3-8 译码器 74LS138，其说明见器件手册或https://baike.baidu.com/item/74LS138/7761037?fr=aladdin
2.利用上面设计的 74LS138 译码器(可能需要多个)，设计一个 4 位二进制8421 码到格雷码的转换器，并在 BASYS3 开发板上实现。其中：
输入：最左侧 4 个 SW 控制 4 位 8421 码的输入
输出：LED 灯与 SW 的输出相对应；4 个七段数码管显示格雷码。
3.利用 04 组合逻辑分析+设计.ppt 上的公式，在开发板上重做上面的题目，并进行仿真验证
代码
Basys3_Master.xdc
## Clock signal
set_property PACKAGE_PIN W5 [get_ports CLK100MHZ]
set_property IOSTANDARD LVCMOS33 [get_ports CLK100MHZ]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK100MHZ]
## Switches
set_property PACKAGE_PIN V17 [get_ports {sw[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
set_property PACKAGE_PIN V16 [get_ports {sw[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
set_property PACKAGE_PIN W16 [get_ports {sw[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
set_property PACKAGE_PIN W17 [get_ports {sw[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
set_property PACKAGE_PIN W15 [get_ports {sw[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
set_property PACKAGE_PIN V15 [get_ports {sw[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
set_property PACKAGE_PIN W14 [get_ports {sw[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
set_property PACKAGE_PIN W13 [get_ports {sw[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
set_property PACKAGE_PIN V2 [get_ports {sw[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
set_property PACKAGE_PIN T3 [get_ports {sw[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
set_property PACKAGE_PIN T2 [get_ports {sw[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
set_property PACKAGE_PIN R3 [get_ports {sw[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
set_property PACKAGE_PIN W2 [get_ports {sw[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
set_property PACKAGE_PIN U1 [get_ports {sw[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
set_property PACKAGE_PIN T1 [get_ports {sw[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
set_property PACKAGE_PIN R2 [get_ports {sw[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
## LEDs
set_property PACKAGE_PIN U16 [get_ports {led[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
set_property PACKAGE_PIN E19 [get_ports {led[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
set_property PACKAGE_PIN U19 [get_ports {led[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
set_property PACKAGE_PIN V19 [get_ports {led[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
set_property PACKAGE_PIN W18 [get_ports {led[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
set_property PACKAGE_PIN U15 [get_ports {led[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
set_property PACKAGE_PIN U14 [get_ports {led[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
set_property PACKAGE_PIN V14 [get_ports {led[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
set_property PACKAGE_PIN V13 [get_ports {led[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
set_property PACKAGE_PIN V3 [get_ports {led[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
set_property PACKAGE_PIN W3 [get_ports {led[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
set_property PACKAGE_PIN U3 [get_ports {led[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
set_property PACKAGE_PIN P3 [get_ports {led[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
set_property PACKAGE_PIN N3 [get_ports {led[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
set_property PACKAGE_PIN P1 [get_ports {led[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
set_property PACKAGE_PIN L1 [get_ports {led[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
##7 segment display
set_property PACKAGE_PIN W7 [get_ports {a2g[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a2g[6]}]
set_property PACKAGE_PIN W6 [get_ports {a2g[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a2g[5]}]
set_property PACKAGE_PIN U8 [get_ports {a2g[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a2g[4]}]
set_property PACKAGE_PIN V8 [get_ports {a2g[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a2g[3]}]
set_property PACKAGE_PIN U5 [get_ports {a2g[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a2g[2]}]
set_property PACKAGE_PIN V5 [get_ports {a2g[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a2g[1]}]
set_property PACKAGE_PIN U7 [get_ports {a2g[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a2g[0]}]
set_property PACKAGE_PIN U2 [get_ports {an[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
set_property PACKAGE_PIN U4 [get_ports {an[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
set_property PACKAGE_PIN V4 [get_ports {an[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
set_property PACKAGE_PIN W4 [get_ports {an[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]mainDesign.sv
module mainDesign(
input logic CLK100MHZ,
input logic [15:0] sw,
output logic [15:0] led,
output logic [3:0] an,
output logic [6:0] a2g
);
logic [3:0] Gray;
assign led[15:12] =sw[15:12];
Gray1 G1(.Bin(sw[15:12]),.Gray(Gray));
X7Seg X1(.clk(CLK100MHZ),.x(Gray),.an(an),.a2g(a2g));
endmodule_74LS138.sv
module _74LS138(
input logic G1,G2A,G2B,
input logic [2:0] A,
output logic [7:0] Y
);
always @(G1,G2A,G2B,A) begin
if({G1,G2A,G2B}==3'b100)begin
case(A)
3'b000: Y=8'b11111110;
3'b001: Y=8'b11111101;
3'b010: Y=8'b11111011;
3'b011: Y=8'b11110111;
3'b100: Y=8'b11101111;
3'b101: Y=8'b11011111;
3'b110: Y=8'b10111111;
3'b111: Y=8'b01111111;
default:Y=8'b11111111;
endcase
end
else Y=8'b11111111;
end
endmoduleBin7Seg.sv
module Bin7Seg(
input logic x,
output logic [6:0] a2g
);
always_comb
case(x)
0: a2g = 7'b0000001;
1: a2g = 7'b1001111;
default: a2g = 7'b0000001; //0
endcase
endmoduleX7Seg.sv
module X7Seg(
input logic clk,
input logic clr,
input logic [3:0] x,
output logic [3:0] an,
output logic [6:0] a2g
);
logic [1:0] s;
logic digit;
logic [19:0] clkdiv;
assign s = clkdiv[19:18];// count every 10.4ms
always_comb
case(s)
0: digit = x[0];
1: digit = x[1];
2: digit = x[2];
3: digit = x[3];
default: digit = x[3:0];
endcase
always_comb
case(s)
0: an = 4'b1110;
1: an = 4'b1101;
2: an = 4'b1011;
3: an = 4'b0111;
default: an = 4'b1110;
endcase
always @(posedge clk, posedge clr)
if(clr == 1) clkdiv <= 0;
else clkdiv <= clkdiv + 1;
Bin7Seg b7(.x(digit),.a2g(a2g));
endmoduleGray1.sv
module Gray1(
input logic [3:0] Bin,
output logic [3:0] Gray
);
logic [7:0] a0LY;
logic [7:0] a1LY;
logic [7:0] a2LY;
logic [7:0] a0RY;
logic [7:0] a1RY;
logic [7:0] a2RY;
_74LS138 a0L(.G1(1),.G2A(Bin[3]),.G2B(0),.A(Bin[2:0]),.Y(a0LY));
_74LS138 a1L(.G1(1),.G2A(Bin[3]),.G2B(0),.A(Bin[2:0]),.Y(a1LY));
_74LS138 a2L(.G1(1),.G2A(Bin[3]),.G2B(0),.A(Bin[2:0]),.Y(a2LY));
_74LS138 a0R(.G1(Bin[3]),.G2A(0),.G2B(0),.A(Bin[2:0]),.Y(a0RY));
_74LS138 a1R(.G1(Bin[3]),.G2A(0),.G2B(0),.A(Bin[2:0]),.Y(a1RY));
_74LS138 a2R(.G1(Bin[3]),.G2A(0),.G2B(0),.A(Bin[2:0]),.Y(a2RY));
assign Gray[0]=!(a0LY[1]&a0LY[2]&a0LY[5]&a0LY[6]&a0RY[1]&a0RY[2]&a0RY[5]&a0RY[6]);
assign Gray[1]=!(a1LY[2]&a1LY[3]&a1LY[4]&a1LY[5]&a1RY[2]&a1RY[3]&a1RY[4]&a1RY[5]);
assign Gray[2]=!(a2LY[4]&a2LY[5]&a2LY[6]&a2LY[7]&a2RY[0]&a2RY[1]&a2RY[2]&a2RY[3]);
assign Gray[3]=Bin[3];
endmodule